/*************************************************************************************************** * Copyright (c) 2023 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved. * SPDX-License-Identifier: BSD-3-Clause * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions are met: * * 1. Redistributions of source code must retain the above copyright notice, this * list of conditions and the following disclaimer. * * 2. Redistributions in binary form must reproduce the above copyright notice, * this list of conditions and the following disclaimer in the documentation * and/or other materials provided with the distribution. * * 3. Neither the name of the copyright holder nor the names of its * contributors may be used to endorse or promote products derived from * this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * **************************************************************************************************/ #pragma once #include "cutlass/gemm/kernel/static_tile_scheduler.hpp" namespace cutlass::gemm::kernel::detail { /////////////////////////////////////////////////////////////////////////////// class StaticPersistentTileScheduler100: public StaticPersistentTileScheduler< StaticPersistentTileScheduler100 > { public: using BaseScheduler = StaticPersistentTileScheduler; public: using BaseScheduler::StaticPersistentTileScheduler; using Params = PersistentTileSchedulerSm90Params; using RasterOrder = typename Params::RasterOrder; using RasterOrderOptions = typename Params::RasterOrderOptions; struct CLCResponse { uint32_t data[4] = {0}; }; static constexpr bool IsDynamicPersistent = false; using Pipeline = PipelineEmpty; using PipelineStorage = typename Pipeline::SharedStorage; using ThrottlePipeline = PipelineEmpty; using ThrottlePipelineStorage = typename ThrottlePipeline::SharedStorage; class SharedStorage { public: CUTLASS_DEVICE PipelineStorage pipeline() { return PipelineStorage{}; } CUTLASS_DEVICE ThrottlePipelineStorage throttle_pipeline() { return ThrottlePipelineStorage{}; } CUTLASS_DEVICE CLCResponse* data() { return nullptr; } }; using WorkTileInfo = typename BaseScheduler::WorkTileInfo; using Arguments = typename BaseScheduler::Arguments; // get work_idx_m, work_idx_n from blk_per_grid_dim while applying swizzle static CUTLASS_DEVICE cute::tuple get_work_idx_m_and_n( uint64_t blk_per_grid_dim, FastDivmodU64Pow2 const& divmod_cluster_shape_major, FastDivmodU64Pow2 const& divmod_cluster_shape_minor, FastDivmodU64 const& divmod_cluster_blk_major, int32_t log_swizzle_size, RasterOrder raster_order) { uint64_t cluster_id, cluster_major_offset = 0 ; divmod_cluster_shape_major(cluster_id, cluster_major_offset, blk_per_grid_dim); uint64_t cluster_idx_minor, cluster_idx_major; uint64_t cluster_idx_minor_div_swizzle, extra, offset; offset = cluster_id & ((1 << log_swizzle_size) - 1); extra = cluster_id >> log_swizzle_size; divmod_cluster_blk_major(cluster_idx_minor_div_swizzle, cluster_idx_major, extra); cluster_idx_minor = cluster_idx_minor_div_swizzle * (1 << log_swizzle_size) + offset; int32_t minor_work_idx, major_work_idx; minor_work_idx = static_cast(cluster_idx_minor * divmod_cluster_shape_minor.divisor); major_work_idx = static_cast(cluster_idx_major * divmod_cluster_shape_major.divisor); if (raster_order == RasterOrder::AlongN) { return {minor_work_idx, major_work_idx}; } else { return {major_work_idx, minor_work_idx}; } } // clc_response_ptr is a placeholder; it is just to make the StaticPersistentTileScheduler100 and PersistentTileScheduler100 constructor interfaces consistent CUTLASS_DEVICE explicit StaticPersistentTileScheduler100(CLCResponse* /* clc_response_ptr */, Params const& params, dim3 block_id_in_cluster) : BaseScheduler(params) {} // The basic tile scheduler does not require any additional workspace template static size_t get_workspace_size(Arguments const&args, ProblemShape, KernelHardwareInfo const&, uint32_t, const uint32_t = 1, uint32_t = 1) { size_t workspace_size = 0; return workspace_size; } template static cutlass::Status initialize_workspace(Arguments const& args, void* workspace_ptr, cudaStream_t stream, ProblemShape problem_shape, KernelHardwareInfo const&, uint32_t, const uint32_t = 1, uint32_t = 1, CudaHostAdapter *cuda_adapter = nullptr) { return Status::kSuccess; } template static Params to_underlying_arguments( ProblemShapeMNKL problem_shape_mnkl, TileShape tile_shape_mnk, AtomThrShape atom_thr_shape_mnk, ClusterShape cluster_shape_mnk, KernelHardwareInfo const& hw_info, Arguments const& arguments, [[maybe_unused]] void* workspace = nullptr, [[maybe_unused]] const uint32_t epilogue_subtile = 1 ) { // We only need the tile and cluster shape during scheduler setup, so let FTAD do the magic static_assert(cute::is_static::value); static_assert(cute::is_static::value); dim3 problem_blocks = BaseScheduler::get_tiled_cta_shape_mnl(problem_shape_mnkl, tile_shape_mnk, atom_thr_shape_mnk, cluster_shape_mnk); Params params; params.initialize( problem_blocks, to_gemm_coord(cluster_shape_mnk), hw_info, arguments.max_swizzle_size, arguments.raster_order ); return params; } template static Params to_underlying_arguments( ProblemShapeMNKL problem_shape_mnkl, TileShape tile_shape, ClusterShape cluster_shape, [[maybe_unused]] KernelHardwareInfo const& hw_info, Arguments const& arguments, [[maybe_unused]] void* workspace=nullptr, [[maybe_unused]] const uint32_t epilogue_subtile = 1, [[maybe_unused]] uint32_t ktile_start_alignment_count = 1u) { // We only need the tile and cluster shape during scheduler setup, so let FTAD do the magic static_assert(cute::is_static::value); static_assert(cute::is_static::value); dim3 problem_blocks = BaseScheduler::get_tiled_cta_shape_mnl(problem_shape_mnkl, tile_shape, cluster_shape); Params params; params.initialize( problem_blocks, to_gemm_coord(cluster_shape), hw_info, arguments.max_swizzle_size, arguments.raster_order ); return params; } template < bool IsComplex, class TiledMma, class AccEngine, class AccLayout, class AccumulatorPipeline, class AccumulatorPipelineState, class CopyOpT2R > CUTLASS_DEVICE AccumulatorPipelineState fixup( TiledMma const& , WorkTileInfo const&, cute::Tensor&, AccumulatorPipeline, AccumulatorPipelineState acc_pipe_consumer_state, CopyOpT2R) const { return acc_pipe_consumer_state; } // Performs the reduction across splits for a given output tile. template CUTLASS_DEVICE static void fixup( Params const& params, WorkTileInfo const& work_tile_info, FrgTensorC& accumulators, uint32_t num_barriers, uint32_t barrier_idx) { } }; }