o
    -wiI                     @   s   d Z ddlZddlmZmZmZmZmZmZ ddl	m
Z
mZmZmZmZmZmZmZmZ g dZG dd deZG dd	 d	eZG d
d deZdS )z
    pygments.lexers.hdl
    ~~~~~~~~~~~~~~~~~~~

    Lexers for hardware descriptor languages.

    :copyright: Copyright 2006-2017 by the Pygments team, see AUTHORS.
    :license: BSD, see LICENSE for details.
    N)
RegexLexerbygroupsincludeusingthiswords)	TextCommentOperatorKeywordNameStringNumberPunctuationError)VerilogLexerSystemVerilogLexer	VhdlLexerc                   @   s  e Zd ZdZdZddgZdgZdgZdZde	j
dfd	efd
efdefde	jfde	jfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefdefdejfdeeejefdeeejed fed!d"d#efed$d%d"d&e	j
fed'd(d"d&ejfed)d"d#ej fd*ej!fd+efgd,ed-fd.ej"fd/efdefd0efgd1e	j
fd2e	jfd3e	jd-fd4e	j
fd5e	j
fd	e	j
d-fgd6ejd-fgd7Z#d8d9 Z$d:S );r   zZ
    For verilog source code with preprocessor directives.

    .. versionadded:: 1.4
    verilogvz*.vztext/x-verilog(?:\s|//.*?\n|/[*].*?[*]/)+^\s*`definemacro\n\s+\\\n/(\\\n)?/(\n|(.|\n)*?[^\\]\n)/(\\\n)?[*](.|\n)*?[*](\\\n)?/[{}#@]L?"string4L?'(\\.|\\[0-7]{1,3}|\\x[a-fA-F0-9]{1,2}|[^\\\'\n])'%(\d+\.\d*|\.\d+|\d+)[eE][+-]?\d+[lL]?(\d+\.\d*|\.\d+|\d+[fF])[fF]?([0-9]+)|(\'h)[0-9a-fA-F]+([0-9]+)|(\'b)[01]+([0-9]+)|(\'d)[0-9]+([0-9]+)|(\'o)[0-7]+\'[01xz]\d+[Ll]?\*/[~!%^&*+=|?:<>/-][()\[\],.;\']`[a-zA-Z_]\w*^(\s*)(package)(\s+)^(\s*)(import)(\s+)import)qalwaysalways_comb	always_ffalways_latchandassign	automaticbeginbreakbufbufif0bufif1casecasexcasezcmosconstcontinuedeassigndefaultdefparamdisabledoedgeelseendendcaseendfunctionendgenerate	endmodule
endpackageendprimitive
endspecifyendtableendtaskenumeventfinalforforceforeverforkfunctiongenerategenvarhighz0highz1ifinitialinoutinputintegerjoinlarge
localparammacromodulemediummodulenandnegedgenmosnornotnotif0notif1oroutputpacked	parameterpmosposedge	primitivepull0pull1pulldownpulluprcmosrefreleaserepeatreturnrnmosrpmosrtranrtranif0rtranif1scalaredsignedsmallspecify	specparamstrengthr    strong0strong1structtabletasktrantranif0tranif1typetypedefunsignedvarvectoredvoidwaitweak0weak1whilexnorxor\bsuffix)
accelerateautoexpand_vectornets
celldefinedefault_nettyperI   elsifendcelldefineendif
endprotectendprotectedexpand_vectornetsifdefifndefr   noacceleratenoexpand_vectornetsnoremove_gatenamesnoremove_netnamesnounconnected_driveprotect	protectedremove_gatenamesremove_netnamesresetall	timescaleunconnected_driveundef`)prefixr   )4bits
bitstorealbitstoshortrealcountdriversdisplayfclosefdisplayfinishfloorfmonitorfopenfstrobefwrite
getpatternhistoryincsaverc   itorkeylistlogmonitor
monitoroff	monitoronnokeynologprinttimescalerandomreadmembreadmemhrealtime
realtobitsresetreset_countreset_valuerestartrtoisavescalescopeshortrealtobits
showscopesshowvariablesshowvars	sreadmemb	sreadmemhstimestopstrobetime
timeformatwritez\$byteshortintintlongintrd   r   bitlogicregsupply0supply1tritriandtriortri0tri1trireguwirewirewandwoshortrealrealr   [a-zA-Z_]\w*:(?!:)\$?[a-zA-Z_]\w*"#pop/\\([\\abfnrtv"\']|x[a-fA-F0-9]{2,4}|[0-7]{1,3})	[^\\"\n]+\\[^/\n]+/[*](.|\n)*?[*]///.*?\n/	(?<=\\)\n	[\w:]+\*?)rootr    r   r0   c                 c   @    t | |D ]\}}}|tu r| rtj}|||fV  qd S Nr   get_tokens_unprocessedr   isupperConstantselftextindextokenvalue r!  ]/home/ubuntu/sommelier/.venv/lib/python3.10/site-packages/wandb/vendor/pygments/lexers/hdl.pyr        
z#VerilogLexer.get_tokens_unprocessedN)%__name__
__module____qualname____doc__namealiases	filenames	mimetypes_wsr	   Preprocr   Single	Multiliner   r   Charr   FloatHexBinIntegerOctr   r
   r   r  r   r   	Namespacer   BuiltinTypeLabelEscapetokensr  r!  r!  r!  r"  r      s    

	
O


	cr   c                   @   s  e Zd ZdZdZddgZddgZdgZdZde	j
d	fd
eeejefdeeejedfdefdefdefde	jfde	jfdefdedfdejfdejfdejfdejfdejfdejfdejfdefdejfdefdefd efd!ejfed"d#d$efed%d#d$e	j
fed&d#d$ejfd'eeed(fed)d#d$ej fd*ej!fd+efgd,ej"d-fgd.ed-fd/ej#fd0efdefd1efgd2e	j
fd3e	jfd4e	jd-fd5e	j
fd6e	j
fde	j
d-fgd7ejd-fgd8Z$d9d: Z%d;S )<r   z
    Extends verilog lexer to recognise all SystemVerilog keywords from IEEE
    1800-2009 standard.

    .. versionadded:: 1.5
    systemverilogsvz*.svz*.svhztext/x-systemverilogr   r   r   r.   r/   r0   r   r   r   r   r   r   r   r    r!   r"   r#   r$   r%   r&   r'   r(   r)   r*   r+   r,   r-   )	accept_onaliasr1   r2   r3   r4   r5   assertr6   assumer7   beforer8   bindbinsbinsofr   r9   r:   r;   r<   r   r=   r>   r?   cellchandlecheckerclassclockingr@   configrA   
constraintcontextrB   cover
covergroup
coverpointcrossrC   rD   rE   designrF   distrG   rH   rI   rJ   rK   
endcheckerendclassendclocking	endconfigrL   rM   endgroupendinterfacerN   rO   rP   
endprogramendpropertyendsequencerQ   rR   rS   rT   rU   
eventuallyexpectexportextendsexternrV   first_matchrW   rX   foreachrY   rZ   forkjoinr[   r\   r]   globalr^   r_   r`   iffifnoneignore_binsillegal_binsimpliesr0   incdirr   ra   rb   rc   insideinstancer   rd   	interface	intersectre   join_any	join_nonerf   letliblistlibrarylocalrg   r   r   rh   matchesri   modportrj   rk   rl   newnexttimerm   rn   noshowcancelledro   rp   rq   nullrr   rs   packagert   ru   rv   rw   rx   priorityprogrampropertyr   ry   rz   r{   r|   pulsestyle_ondetectpulsestyle_oneventpurerandrandcrandcaserandsequencer}   r  r   r~   r   	reject_onr   r   restrictr   r   r   r   r   r   s_alwayss_eventually
s_nexttimes_untils_until_withr   sequencer   	shortrealshowcancelledr   r   solver   r   staticr    strongr   r   r   superr   r   sync_accept_onsync_reject_onr   taggedr   r   
throughoutr   timeprecisiontimeunitr   r   r   r   r   r   r   r   r  r   r   unionuniqueunique0r   until
until_withuntypeduser  r   r   virtualr   r   
wait_orderr  weakr   r   r   wildcardr  withwithinworr   r   r   r   )z	`__FILE__z	`__LINE__z`begin_keywordsz`celldefinez`default_nettypez`definez`elsez`elsifz`end_keywordsz`endcelldefinez`endifz`ifdefz`ifndefz`includez`linez`nounconnected_drivez`pragmaz	`resetallz
`timescalez`unconnected_drivez`undefz`undefineall)Lz$displayz	$displaybz	$displayhz	$displayoz$dumpallz	$dumpfilez
$dumpflushz
$dumplimitz$dumpoffz$dumponz
$dumpportsz$dumpportsallz$dumpportsflushz$dumpportslimitz$dumpportsoffz$dumpportsonz	$dumpvarsz$fclosez	$fdisplayz
$fdisplaybz
$fdisplayhz
$fdisplayoz$feofz$ferrorz$fflushz$fgetcz$fgetsz$finishz	$fmonitorz
$fmonitorbz
$fmonitorhz
$fmonitoroz$fopenz$freadz$fscanfz$fseekz$fstrobez	$fstrobebz	$fstrobehz	$fstrobeoz$ftellz$fwritez$fwritebz$fwritehz$fwriteoz$monitorz	$monitorbz	$monitorhz	$monitoroz$monitoroffz
$monitoronz	$plusargsz$randomz	$readmembz	$readmemhz$rewindz$sformatz	$sformatfz$sscanfz$strobez$strobebz$strobehz$strobeoz$swritez$swritebz$swritehz$swriteoz$testz$ungetcz$value$plusargsz$writez$writebz$writehz
$writemembz
$writememhz$writeoz(class)(\s+)	classnamer   r  r  z[a-zA-Z_]\w*r
  r	  r  r  r  r  r  r  r  r  r  )r  r  r    r   r0   c                 c   r  r  r  r  r!  r!  r"  r    r#  z)SystemVerilogLexer.get_tokens_unprocessedN)&r$  r%  r&  r'  r(  r)  r*  r+  r,  r	   r-  r   r   r   r6  r.  r/  r   r   r0  r   r1  r2  r3  r4  r5  r   r
   r   r  r   r7  r8  r9  Classr:  r;  r  r!  r!  r!  r"  r      s    
 !#
a


	xr   c                   @   s  e Zd ZdZdZdgZddgZdgZej	ej
B Zdefdefdefd	ejfd
ejfdefdejfdefdefdeeeejfdeeeefdeeeejefdeeeejfdeejejfedddejfdeeeejfdeeeejeeeejee	fdeejeeefdeeeedfedededdefgeddejfd efd!ed"fged#ddejfged$ddefgd%ejfd&ejfd'ej fd(ej!fd)ej"fd*ej#fgd+Z$d,S )-r   z:
    For VHDL source code.

    .. versionadded:: 1.5
    vhdlz*.vhdlz*.vhdztext/x-vhdlr   r   r   z--.*?$z'(U|X|0|1|Z|W|L|H|-)'r+   z
'[a-z_]\w*r,   z"[^\n\\"]*"z(library)(\s+)([a-z_]\w*)z(use)(\s+)(entity)z(use)(\s+)([a-z_][\w.]*\.)(all)z(use)(\s+)([a-z_][\w.]*)z(std|ieee)(\.[a-z_]\w*))stdieeeworkr   r   z"(entity|component)(\s+)([a-z_]\w*)zN(architecture|configuration)(\s+)([a-z_]\w*)(\s+)(of)(\s+)([a-z_]\w*)(\s+)(is)z ([a-z_]\w*)(:)(\s+)(process|for)z
(end)(\s+)endblocktypeskeywordsnumbersz	[a-z_]\w*z(\s+);r
  )booleanr   	characterseverity_levelrd   r   delay_lengthnaturalpositiver    
bit_vectorfile_open_kindfile_open_status
std_ulogicstd_ulogic_vector	std_logicstd_logic_vectorr   r   )_absaccessafterr?  allr5   architecturearrayr@  	attributer8   blockbodybufferbusr=   	componentconfigurationconstant
disconnectdowntorI   r   rJ   entityexitfilerW   r[   r\   genericgroupguardedr`   impureininertialrb   islabelrt  linkageliteralloopmapmodrk   rx  nextrn   ro   r{  ofonopenrr   othersoutr|  port	postponed	procedureprocessr  rangerecordregisterrejectremr   rolrorselectseveritysignalsharedslasllsrasrlsubtypethento	transportr   unitsr  r  variabler   whenr   r  r   r   z\d{1,2}#[0-9a-f_]+#?z\d+z(\d+\.\d*|\.\d+|\d+)E[+-]?\d+zX"[0-9a-f_]+"z
O"[0-7_]+"z	B"[01_]+")r  r  r  r  r  N)%r$  r%  r&  r'  r(  r)  r*  r+  re	MULTILINE
IGNORECASEflagsr   r	   r.  r   r0  r
   r   	Attributer   r   r   r6  r   r  r   r   r   r8  r   r4  r1  r2  r5  r3  r;  r!  r!  r!  r"  r   !  s    
'	
r   )r'  r  pygments.lexerr   r   r   r   r   r   pygments.tokenr   r	   r
   r   r   r   r   r   r   __all__r   r   r   r!  r!  r!  r"  <module>   s   
 ,{ 